Field of the Invention
The present invention relates to an image coding apparatus, an image coding method, and a recording medium, and an image decoding apparatus, an image decoding method, and a recording medium. In particular, the invention relates to a coding method and a decoding method for an image in which respective pictures are divided into rectangular tiles.
Description of the Related Art
With a current progress in digital technologies, digital moving image capturing at a high resolution in a digital camera and a digital video camera is widely spread. The digital moving image is generally compressed (coded) to be efficiently recorded in a recording medium represented by a flash memory, and H.264/MPEG-4 AVC (hereinafter, which will be referred to as H.264) is widely used as a coding system for the moving image.
In recent years, an activity for setting an international standardization of a further more efficient coding system as a succession of H.264 has started, and Joint Collaborative Team on Video Coding (JCT-VC) has been established between ISO/IEC and ITU-T. In JCT-VC, a standardization of High Efficiency Video Coding system (hereinafter, which will be referred to as HEVC) has been progressed.
FIG. 10 illustrates a processing order in coding processing in the HEVC. As illustrated in FIG. 10, the coding processing is performed by dividing one picture in units of coding tree blocks (hereinafter, which will be referred to as CTB) corresponding to a previously set square composed of 64 pixels×64 pixels or the like. The coding is sequentially performed in the picture from the CTB on the upper left→the upper right→the bottom left→the bottom right (raster scan order), and a coding stream (hereinafter, which will be simply referred to as stream) is output. In decoding processing, decoding is performed in the same processing order as the coding processing, and a decoded image is output.
For the standardization of the HEVC, various coding tools are widely reviewed in terms of a facility of the mounting and a reduction in the processing time as well as an improvement in the coding efficiency. Among them, parallel processing of coding and decoding, a technique called slice division for dividing one picture in the coding order in a horizontal direction for purposes of increasing an error resilience and the like, a technique called tile division for dividing one picture into rectangular areas, and the like are proposed (JCT-VC contribution, JCTVC-M1005-v1.doc, the Internet <http://phenix.int-evry.fr/jct/doc_end_user/documents/13_Incheon/wg11/>: Non-patent Document 1).
Speeding-up by the parallel processing of coding and decoding is realized by using the slices or the tiles, and also the amount of memory used for a coding program and a decoding program can be reduced. According to the HEVC, these slice division and tile division can also be used in combination.
In addition, Non-patent Document 1 describes a technique called Motion-Constrained Tile Sets (MCTS) in which the above-described tile division is utilized, and only a part of tiles can be independently decoded from a picture having a continuous stream. In this MCTS, a tile set constituted by one or more tiles within the picture is defined, and only this tile set can be reproduced as a partial moving image from the coded stream.
When an MCTS supplemental enhancement information (SEI) message is included in the stream, the coding is performed under the following restrictions in this video sequence.                The coding is performed while a similar tile division is used by each picture in the video sequence.        The coding is performed while similar tile sets used in all the pictures in the video sequence. That is, sizes and positions of the tile sets are the same in all the pictures.        With regard to the MCTS coding, the coding is not performed by using a motion vector that uses a reference pixel outside the relevant tile set on a reference picture.        
In the decoding, in a case where this MCTS SEI message is included in the stream, it is possible to extract only the tile set designated as the MCTS from the continuous picture to be decoded and reproduced as the partial moving image at a high speed. By using the MCTS, for example, it is possible to realize a region of interest (ROI) in which only a region of interest set by a user is decoded at a high speed.
When a moving image constituted by one or more picture groups at a high resolution like horizontal 4096 pixels×vertical 2048 pixels (hereinafter, which will be described as 4096×2048 pixels) is decoded, the decoding can be desirably performed in parallel by using a plurality of image decoding apparatuses. For example, if a picture having 4096×2048 pixels can be decoded in parallel by using four image decoding apparatuses provided with a processing capability of 2048×1024 pixels, reuse of the image decoding apparatuses is facilitated, and it is possible to realize a cost reduction.
FIG. 8 illustrates an example of an image decoding system using the plurality of image decoding apparatuses. Each of image decoding apparatuses 801 is provided with a DRAM 803 corresponding to a memory outside a chip and an SRAM 802 corresponding to a memory inside the chip. Data transfer between the image decoding apparatuses 801 is connected by an inter-chip communication apparatus 804. It is noted that an interface for inputting a stream and an interface for outputting a decoded image are omitted from FIG. 8, and a description thereof is also omitted.
As described above, in the HEVC, the coding and decoding are performed in the raster scan order in units of the CTB within the picture in principle. Furthermore, in the HEVC, like an intra prediction or the like, a plurality of processing where a reference is made to a pixel of an upwardly adjacent CTB or a coding parameter exist in the processing on the processing target CTB. To refer to the pixel of the upwardly adjacent CTB or the coding parameter, a horizontal line buffer for holding a capacity for one line is to be used. When the image decoding apparatuses are mounted as a system LSI, this horizontal line buffer is mounted as the SRAM 802 of FIG. 8 in general, and when the picture having a high resolution like 4096×2048 pixels is set as a decoding target, the SRAM 802 having a large capacity is to be used.
For example, a case where a stream is decoded in which the picture having 4096×2048 pixels is divided by a tile division into four pieces of tile sets having 4096×512 pixels will be supposed. In order that the respective tile sets are decoded in parallel by the four image decoding apparatuses 801, each of the image decoding apparatuses 801 is to be provided with the horizontal line buffer corresponding to 4096 pixels as the SRAM 802, and a problem occurs that a memory cost is increased.
The tiles decoded by the respective image decoding apparatuses 801 in FIG. 8 are written to the DRAM 803. On the other hand, when the picture is divided into tile sets and the plurality of tile sets are decoded in parallel by the plurality of image decoding apparatuses 801, a motion vector that refers to pixels in different tile sets on the reference picture may be used in some cases in a motion compensation.
When the above-described stream is decoded, each of the image decoding apparatuses 801 is to refer to not only the decoding pixels on the tile sets on the DRAM 803 connected to itself but also the decoding pixels on the tile sets recorded on the DRAMs 803 connected to the other image decoding apparatuses 801. To refer to data on the DRAMs corrected to the other image decoding apparatuses 801 in FIG. 8, the inter-chip communication apparatus 804 is used. The inter-chip communication apparatus 804 is desirably not used because the cost is high and the power consumption is high in general.
When the picture is divided into the tile sets as described above and the respective divided tile sets are decoded in parallel by the plurality of image decoding apparatuses 801 too, problems occur that a memory cost is increased and the power consumption by the inter-chip communication apparatus 804 is increased.
The present invention is proposed in view of the above-described issues and aims at reducing memory costs of respective image decoding apparatuses and power consumption by an inter-chip communication apparatus in a use case in which a picture having a high resolution is decoded in parallel by using a plurality of image decoding apparatuses.